1. Field of the Invention
The present invention relates to an amplifier circuit that samples input signals and outputs signals obtained by applying a gain to the sampled input signals having different voltages.
2. Description of the Related Art
In video equipment using a solid-state image pickup device such as a CCD (Charge Coupled Device), a correlation double sampling circuit (CDS) and a variable gain amplifier circuit (PGA) are used so that the noise of a video signal from the solid-state image pickup device is eliminated and the signal itself is amplified with a prescribed gain. In the CDS and PGA, an amplifier circuit composed of a switched capacitor circuit is conventionally used. For example, Patent Document 1 describes a differential amplifier circuit composed of a switched capacitor circuit.
FIG. 1 shows the conventional differential amplifier circuit composed of the switched capacitor circuit. The differential amplifier circuit 10 shown in FIG. 1 is composed of a full differential amplifier circuit 11, switches SW1, SW2, SW3, SW4, SW5, SW6, SW7, and SW8, and capacitors Cs and Cf. The differential amplifier circuit 11 is connected to, for example, an external device 12 that outputs signals to be amplified. The external device 12 represents, for example, a solid-state image pickup device that outputs video signals to be amplified. The operations of the differential amplifier circuit 11 are described below.
At a sampling operation in the differential amplifier circuit 11, the switches SW1, SW2, SW4, SW5, and SW8 are turned on, and the switch SW3 is turned off. A reference voltage Vref2 is supplied to the switches SW6 and SW7. At this time, signals output from the external device 12 are input to input terminals Vip and Vim, and an electrical charge corresponding to a potential difference between a standard voltage Vref1 and the input signals is stored in the capacitors Cs. Furthermore, both outputs from the full differential amplifier circuit 11 are short-circuited by the switch SW8, and an electrical charge corresponding to a potential difference between the standard voltage Vref1 and the reference voltage Vref2 is stored in the capacitors Cf via the switches SW6 and SW7.
Then, when the sampling operation is completed to establish a signal output state, the switches SW1, SW2, SW4, SW5, and SW8 are turned off, and the switch SW3 is turned on. The switches SW6 and SW7 are connected to the outputs of the full differential amplifier circuit 11. At this time, the one terminal of the capacitors Cs is short-circuited to have the same potential as the other terminal thereof, which in turn moves the electrical charges stored in the capacitors Cs to the capacitors Cf. Accordingly, a potential difference Vop−Vom in the outputs of the full differential amplifier circuit 11 is calculated according to the following formula.Vo=Vop−Vom=Cs/Cf×{(Vip−Vref1)−(Vim−Vref1)}=Cs/Cf×(Vip−Vim)  (1)
From the above formula (1), it is found that the gain of the full differential amplifier circuit 11 in the amplifier circuit 10 is determined by the ratio of the capacitors Cs to the capacitors Cf.
Patent Document 1: JP-A-2006-174091
However, the above formula (1) according to the conventional art does not take the offset voltage Voff of the full differential amplifier circuit 11 into consideration, but it includes an error as shown in the following formula (2).Vo=Vop−Vom=Cs/Cf×(Vip−Vim+Voff)  (2)